Modern semiconductor manufacturing processes require that metal busses, nets, wires, and various other structures that are larger than a certain size be slotted. Slotting metal includes creating holes in these metal structures so that the end result resembles a mesh or waffle like pattern. The metal line is then no longer contiguous. Rules for metal slotting are typically complex. There is typically a minimum and maximum size for a slot (hole), for spacing between slots, and for spacing of the furthermost slot to the metal boundary. Other more complex rules can apply and are process specific.
Typically, the criteria that is used to establish if a metal wire must be slotted, is defined in terms of metal width and metal length. If any metal wire found in a semiconductor design is wider than width W, and at the same time, longer than length L, it must be slotted. Length L is defined to be in the same direction as the current flow. Width W is defined to be perpendicular to the current flow. L and W parameters apply to contiguous sections of metal on the same layer. FIG. 1 is a diagram illustrating the metal slotting definition applied to three metal wires A, B, and C. Metal wire A does not require slotting because its width and length are less than the width and length constraints (W, L), while metal wire B and C require slotting because their dimensions exceed the width and length constraints.
When a metal wire exceeds the width and length constraints, the wire is slotted by creating square holes, known as slots, inside the metal area of the wire. FIG. 2 is a diagram illustrating a metal wire 10 both before and after slots 12 are created during the slotting process.
Additionally, many constraints are imposed on the design rules for these metal slots 12, as shown in FIG. 3. Slot design rule constraints include rules for the minimum and maximum length of a slot 12 (sL), the minimum and maximum width of a slot 12 (sW), minimum and maximum spacing between slots 12 (sS), minimum and maximum between the outermost slot and the metal boundary (sB), minimum and maximum alignment between neighboring slots 12 (sA), and minimum and maximum spacing between the edge of any slot 12 and the edge of coincident metal wires (sC). Note that lengths are measured parallel to the direction of current flow in a wire, and widths are measured perpendicular.
Density constraints are also imposed, requiring that the area of slots 12 as a percentage of the total metal wire area, should be within minimum and maximum values. Actual values for all these parameters, as well as precise definitions, will vary according to specific semiconductor fabrication processes. Additionally, some processes may impose further slotting constraints than those defined here.
During semiconductor chip design, it is often necessary to create metal structures, which owing to their width, length, or other topology constraint, become subject to metal slotting rules. The challenge has been to create semiconductor chips that by design must use large metal, which is subject to slotting rules, and to find a means to automatically slot these metal objects. In such cases, a solution is required to create slots in the metal structure in the following manner:    1. Owing to the number of metal structures that could require slotting in a modern semiconductor chip, the metal slotting solution should be automated.    2. The solution should meet the metal slotting rules.    3. The solution should be integrated in the design flow, simple to use, and be generic enough to adapt to slotting rule changes.    4. It should be possible to account for the electrical impact of removing metal to meet slotting rules. The impact should be seen as early in the design flow as possible.    5. There are many physical combinations to slot a given metal structure, all of which will still meet slotting rules. Chip or circuit designers may have specific preferences on how a given metal structure should be slotted. Adequate control of the exact slotting solution for each metal object should be provided.    6. The solution must be capability of handling complex metal topologies, including metal structures of multiple vertices where each vertex as a unique wire width.
Currently, there are several slotting approaches that attempt to meet the above requirements. One approach is to simply avoid having to perform slotting. Where possible in the chip design, metal structures are created to be sufficiently narrow or short, such that they do not require metal slotting. The advantage of this approach of course is that no metal slotting is required, therefore no solution to metal slotting is required. One disadvantage is that restricting chip and circuit designers to create metal structure smaller than certain topologies will limit electrical performance, density, and many other design considerations. In practice, it is not a complete solution. Another disadvantage is that if metal slotting rules change, such that metal width and/or length thresholds are reduced, design practices for avoidance must be changed. This is not a sustainable solution since existing cells and chips must be entirely redesigned.
Another slotting approach is referred to as post-processing automation. Post-processing automation approaches may be performed manually or automatically with a software tool in which all metal objects in a design database are examined to determine which subset of objects are sufficiently large to require slotting.
FIG. 4 is a diagram illustrating example metal objects before post-processing automation. One metal wire 10a is of sufficient size to require metal slotting, while the other metal wire 10b is not. For the metal wire 10a requiring slotting, the tool inserts slots 12 in to the metal wire 10a to meet required slotting rules, as shown in FIG. 5, which shows the metal wire 10a after post-processing automation. This tool can only be run after all metal wiring for the entire chip-layout is complete.
The post-processing automation approach has several disadvantages. First, post-processing automation tools are challenged when dealing with metal structures containing multiple vertices and/or multiples widths. This is because slotting rules typically require that slots must be aligned in at least one direction around a metal bend. Respecting this alignment often violates metal slot-to-metal boundary rules.
FIG. 6 is a diagram illustrating possible violations of slot design rule constraints for a metal wire having multiple vertices. Slot 2 may be governed by rule that states that slot 2 must aligned with slot 1. If this rule is met, however, slot 2 may then violate a slot boundary (sB) rule that requires a slot to be within a minimum/maximum distance to the metal boundary, as shown. If additional slots are introduced, then slot-to-slot spacing (sS) rules may also be violated, as shown for slots 3, 4, and 5.
Another disadvantage is that post-processing automation is further challenged with structures containing multiple staircased edges, or non-mahattan polygons. It is not uncommon to see automation methods violate one slotting rule while trying to meet another. FIG. 7 is a diagram illustrating a metal structure have staircase or non-manhattan shaped boundaries. With such a structure, one or more slotting rules sA, sB, sC, sS, sL, and sW may be violated while the tools attempts to meet others.
Significant algorithm design, and automation development is required to support these complex scenarios. The disadvantage is that the algorithms must be adjusted and tools updated when new metal routing scenarios are encountered.
Even if an automation tool is able to meet the complexities of such metal topologies, another disadvantage is that the process of metal slotting can remove any vias present in the slotting area because the tool may have no means to control how vias are removed.
FIG. 8A is a diagram showing vias 14 on a metal structure 16 pior to post-processing automation, and FIG. 8B is a diagram showing the metal slotting solution intended by a designer. FIG. 8C shows the metal slotting solution chosen by tool, which removes critical vias 14. This may be undesirable to the circuit designer who may have preferred an alternate slotting layout that kept the vias 14 intact in critical areas.
Another drawback to post-processing slotting tools is that it is difficult to predict the electrical impact of slotting metal; this can only be done after the fact. This makes it difficult to plan for the electrical impacts such as resistance, inductance, and capacitance ahead of time, such as during early stages of the chip development or even during the development of the technology itself. This means that the design must be re-timed and reanalyzed to ensure it is meeting electrical constraints. This increases the number of iterations through timing closure or electrical analysis flows.
According, what is needed is an improved approach for creating slotted metal during semiconductor fabrication. The present invention addresses such a need.